This invention relates generally to the presentation of information on a video display and more specifically is directed to pixel/bit mapping on the faceplate of a video display for presenting alphanumeric character and graphics information thereon.
The inside face of a cathode ray tube (CRT) is coated with phosphor, or a similar light-emitting substance, in the form of individual pixels, or dots, which glow when struck by an electron beam. A complete image is generated on the CRT's screen, or faceplate, by scanning the screen with an electron beam generally in a left to right direction as viewed from the front of the video display in an individual line sequence where the electron beam is deflected downward one line at the end of one sweep to again provide another sweep line from left to right. Thus, when the movement of the electron beam across one horizontal scan line is complete, it drops down to the next horizontal scan line and sweeps across this line from left to right. When the electron beam scan reaches the bottom of the CRT's screen, the electron beam is deflected from the lower right hand corner of the screen to the upper left hand corner thereof in a vertical deflection period. During this interval the electron beam is "off" and the vertical deflection of the beam is thus not seen by the viewer.
When utilized in a computer terminal, the video display on the CRT is accomplished by a mapping process wherein memory bits representing the CRT's screen are stored in a random access memory (RAM). Each memory bit has a logical value of one or zero with each bit thus representing a light or dark spot at a particular location on the raster of the video display, depending on the bit's value. Alternatively, a group of bits may be used to represent a gray scale code. In addition, several video RAM's may be utilized in a multi-electron beam video display to provide presentation of color images on the CRT's screen.
In a typical computer terminal with a video display, each alphanumeric character may be thought of as occupying a rectangular "frame" on the CRT's screen. This "frame" may be defined by a rectangular matrix comprised of m by n pixels, or elemental dots. For example, a character "frame" may be 8 by 10 pixels. Within this frame there are 2.sup.80 possible patterns of pixels when each pixel may be on or off. Often, the full flexibility of displaying any of these patterns is not required. In such a case, 8 bits may be used to represent the pattern to be displayed in this frame. This means that only 256 of the potential 2.sup.80 frames may be displayed. This set of displayable patterns is termed the font. Once patterns to represent each of the displayable alphanumeric characters have been defined, the remaining patterns to be included within the font are chosen to facilitate "block-graphic" displays. Since only a very restricted, and usually rigid, subset of the total potential frames may be represented, the "block-graphics" rendered from such a terminal are somewhat inflexible. As has been stated, this is because not all of the potentially displayable patterns may be displayed. To solve this problem, each of the displayable pixels making up the previously described frame may be mapped into a bit of Random Access Memory (RAM). This means that 80 bits of RAM are now required to represent the previously described "frame", and in return, all 2.sup.80 patterns are displayable.
The video display system just described is generally termed "bit-mapped". This is because each bit of the screen is mapped into a bit of RAM. This lies in contrast to the first system which is generally termed as a "character generation" video system because only predefined patterns, or characters, are displayable. It is precisely the mapping of video RAM bits to screen pixels in a bit-mapped video system with which this invention is concerned.
The primary disadvantages of a bit-mapped video system such as that just described are increased cost and complexity. Whereas the former "character-generator" system (with a restricted font), used only 8 bits of RAM to represent the data to be displayed in a "frame", the bit-mapped system uses 80 bits. The increased cost and concomitant complexity has historically rendered such bit-mapped systems quite expensive. However, in the system herein described, the complexity has been significantly reduced by utilizing semiconductor devices readily available for the implementation of character generation systems in the implementation of the desired "bit-mapped" system. This reduces system complexity and cost, though not the amount of RAM required in such a system--the RAM size is generally determined by the number of pixels to be represented on the screen.
The additional cost and complexity attendant with a bit-mapped video system are not limited to hardware implementation issues. The software required to manipulate the data is more complex. In the character generation system, manipulating the 8 bits required to display a character is relatively simple as compared to the manipulation of the 80 bits required to represent a character in the discussed bit-mapped system. Approaching the performance of the much simpler character generator systems from a displayable character rate with a bit-mapped graphics system is difficult, and is closely tied to the mapping of the RAM bits to screen pixels. A "convenient" of such a system. The pixels must be organized conveniently for access in the groups of 80 as required in the display of alphanumeric characters. The pixels must also be organized conveniently for access individually as in the case of displaying a thin "pixel line" across the screen. The invention herein documented provides such a convenient mapping. It facilitates the efficient displaying of characters, as well as addressing individual pixels.
Thus, when this mapping system is used in conjunction with the discussed bit-mapped implementation using "character-generator" type devices, a cost effective, yet flexible, and efficient bit-mapped system is produced. The character "throughput" rates of this system more closely approximate those of the simpler system than they would if the mapping algorithm were not used. Thus, the primary goal/achievement of this invention is higher throughput, i.e., better performance in a more cost effective implementation.
Various attempts have been made in microcomputer terminals to decrease information processing time while simultaneously reducing system complexity and associated cost. For example, one solution is to limit the complexity of the tasks performed by the microcomputer. The number of individual operations required to perform the simpler tasks would be less and would, therefore, take less time. This solution is undesirable in that it would result in a severe limitation in the processing capability of the microcomputer and the entire system. Another approach to the processing time problem has been to increase the throughput of the microcomputer, i.e., to increase the size (e.g., number of bits) of the data word the microcomputer is capable of operating on. For example, if the microcomputer is designed to handle 8-bit data words (as most presently available microcomputers are), a microcomputer capable of handling 12- or 16-bit words is provided. As the word size handled by the microcomputer increases, the complexity, size and cost of the microcomputer also increase at a substantially faster rate. In addition, the present advantages of currently available large-scale, single-chip programmable microcomputers which are powerful, inexpensive, and easy-to-use devices would be lost by going to higher bit word capable machines.
Another problem inherent in a bit-mapping microcomputer controlled video display system relates to the differences between alphanumeric character presentation and video display graphics. As previously explained, alphanumeric characters are presented in a regular, repeating, sequential fashion as the electron beam raster scans the CRT's screen. However, graphics applications typically require the display of seemingly unrelated, widely displaced portions of the CRT's screen. The bit-map addressing in the video RAM in the latter application are substantially more intricate as is the handling of data in displaying graphics information. In addition to the additional complexities of data handling, video display of alphanumeric characters such as in word processing applications generally requires greater display resolution than the presentation of other types of graphics information. Heretofore this enhanced resolution has been available only in substantially more complex and expensive systems.
One approach to improving CRT character generation and display is described in U.S. Pat. No. 4,298,867 to Craig wherein the rise and fall times of an interpolated raster control signal are modified by a rise-time control circuit so as to be proportional to the width of a jagged edge of a character to be displayed. By thus controlling the rise and fall times of the raster control signal as the electron beam strikes the phosphor CRT's screen, gradual changes occur within a time that is proportional to the secant of the slope of the character edge, relative to vertical. This process creates the appearance of a smooth sloping edge when the character is ultimately displayed on the CRT's screen. U.S. Pat. No. 4,298,931 to Tachiuchi, et al., discloses a character pattern display system wherein a plurality of character store RAMs are operated by a central processing unit (CPU) and a display timing signal means. During one character display time, a first character store RAM is subjected to a read/write operation by the CPU. At this time, a second character store RAM is subjected to a read operation by a display timing signal from the display timing signal means and a third character store RAM is refreshed. These concurrent operations of the RAMs are sequentially switched for each character display time. While this system requires sophisticated timing circuitry and a large address memory capacity, it is asserted that this approach provides for the constant display of characters on the CRT's screen using currently available MOS LSI CPU's and RAM's.